Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate or workpiece, and patterning the various layers using lithography to form circuit components and elements thereon.
One or more metallization layers are typically used to connect circuit components and elements together and to contact pads that may be used for external connection to the integrated circuit. If two or more metallization layers are used, vias are typically used to connect the metallization layers together. For example, a via may be used to connect a conductive line in a first metallization layer to a conductive line in an overlying second metallization layer. Vias are also used to connect through insulating layers to underlying circuit components and elements. For example, a via may be used to connect a circuit component to a conductive line in an overlying metallization layer. Vias may also be used to connect conductive lines or circuit components to contact pads and/or bond pads, for example.
Vias can be challenging to pattern, because they typically are quite small, and may comprise a minimum feature size of a semiconductor device in some applications, for example. As feature sizes become smaller and smaller, as is the trend in the semiconductor industry, via formation becomes even more challenging.
Damascene techniques are often used to form vias. In a damascene technique, a dielectric material is deposited on a wafer, and then the dielectric material is patterned with the desired via pattern. The dielectric material may be patterned by depositing a photoresist, patterning the photoresist with the desired via pattern, and using the photoresist as a mask to pattern the dielectric material, for example. The via pattern typically comprises a plurality of trenches, holes, or apertures, for example. The via pattern is then filled in with a conductive material, and a chemical-mechanical polish (CMP) process is used to remove the excess conductive material from the top surface of the dielectric material, leaving a plug or via of conductive material in the via pattern. The conductive material remaining within the dielectric material comprises the via. Conductive lines and vias in metallization layers are often formed using a damascene technique, for example.
A problem in prior art methods of etching via patterns in dielectric materials is the formation of photoresist scum on the sidewalls and the bottom surfaces of the via trenches being formed. The photoresist scum can cause the formation of oxides in undesired regions within the via trenches, resulting in increased resistance of the via. Lengthy cleaning processes may be required in an attempt to remove the photoresist scum from within the via trenches. Photoresist scum increases the cost of manufacturing and may decrease product yields.
Thus, what are needed in the art are methods of eliminating and preventing photoresist scum in semiconductor device manufacturing.